general description the DS28CN01 combines 1024 bits of eeprom withchallenge-and-response authentication security imple- mented with the federal information publications (fips) 180-1/180-2 and iso/iec 10118-3 secure hash algorithm (sha-1). the memory is organized as four 32-byte pages. data copy protection and eprom emu- lation features are supported for each memory page. each DS28CN01 has a guaranteed unique facto ry-pro- grammed 64-bit registration number. communication with the DS28CN01 is accomplished through an industry-standard i 2 c-compatible and smbus -compatible interface. the smbus timeout feature resets thedevice? interface if a bus-timeout fault condition is detected. applications pcb unique serializationaccessory and peripheral identification equipment registration and license management network node identification printer cartridge configuration and monitoring medical sensor authentication and calibration system intellectual property protection features ? 1024 bits of eeprom memory partitioned intofour pages of 256 bits ? dedicated hardware-accelerated sha-1 enginefor generating sha-1 macs ? eeprom memory pages can be individuallycopy protected or put into eprom mode (program from 1 to 0 only) ? write access requires knowledge of the secretand the capability of computing and transmitting a 160-bit mac as authorization ? unique, factory-programmed, and tested 64-bitregistration number assures absolute traceability because no two parts are alike ? endurance 200,000 cycles at +25? ? serial interface user programmable for i 2 c bus and smbus compatibility ? supports 100khz and 400khz i 2 c communication speeds ? +5.5v tolerant interface pins ? operating ranges: +1.62v to +5.5v, -40? to +85? ? 8-pin ?op package DS28CN01 1kb i 2 c/smbus eeprom with sha-1 engine ________________________________________________________________ maxim integrated products 1 sop 2 7 n.c. ad1 18 v cc ad0 scl n.c. 3 6 sda gnd 4 5 DS28CN01 top view + pin configuration ordering information rev 2; 11/09 for pricing, delivery, and ordering information, please contact maxim direct at 1-888-629-4642, or visit maxim? website at www.maxim-ic.com. abridged data sheet + denotes a lead(pb)-free/rohs-compliant package. t = tape and reel. part temp range pin-package DS28CN01u-a00+ -40c to +85c 8 sop DS28CN01u-a00+t -40c to +85c 8 sop typical operating circuit appears at end of data sheet. smbus is a trademark of intel corp. downloaded from: http:///
DS28CN01 1kb i 2 c/smbus eeprom with sha-1 engine 2 _______________________________________________________________________________________ abridged data sheet absolute maximum ratingselectrical characteristics (t a = -40? to +85?.) (note 1) stresses beyond those listed under ?bsolute maximum ratings?may cause permanent damage to the device. these are stress ratings only, and functional operation of the device at these or any other conditions beyond those indicated in the operational sections of the specifications is not implied. exposure to absolute maximum rating conditions for extended periods may affect device reliability. voltage range on any pin relative to ground.........-0.5v to +6v maximum current on any pin ...........................................?0ma operating temperature range ...........................-40? to +85? junction temperature ......................................................+150? storage temperature range .............................-55? to +125? soldering temperature...........................refer to the ipc/jedec j-std-020 specification. parameter symbol conditions min typ max units supply voltage v cc 1.62 5.50 v standby current i ccs bus idle, v cc = +5.5v 5.5 a operating current i cca bus active at 400khz, v cc = +5.5v 500 a power-up wait time t poip (note 2) 5 s eeprom v cc 2.0v 10 programming time t prog v cc < 2.0v 45 ms programming current i prog v cc = +5.5v 1.2 ma at +25c 200,000 endurance (notes 3, 4, 5) n cy at +85c 50,000 data retention (notes 6, 7, 8) t dr at +85c 40 years sha-1 engine sha-1 computation time t csha see full version of the data sheet. ms sha-1 computation current i lcsha see full version of the data sheet. ma scl, sda, ad1, ad0 pins (noes 9, 10) v cc 2.0v -0.3 0.3 v cc low-level input voltage v il v cc < 2.0v -0.3 0.25 v cc v v cc 2.0v 0.7 v cc v ccmax + 0.3v high-level input voltage v ih v cc < 2.0v 0.8 v cc v ccmax + 0.3v v v cc 2.0v 0.05 v cc hysteresis of schmitt trigger inputs (note 2) v hys v cc < 2.0v 0.1 v cc v v cc 2.0v 0.4 low-level output voltage at 4ma sink current, open drain v ol v cc < 2.0v 0.2 v cc v downloaded from: http:///
DS28CN01 note 1: specifications at -40? are guaranteed by design and characterization only and not production tested. note 2: guaranteed by design, characterization, and/or simulation only and not production tested. note 3: this specification is valid for each 8-byte memory row. note 4: write-cycle endurance is degraded as t a increases. note 5: not 100% production tested; guaranteed by reliability monitor sampling. note 6: data retention is degraded as t a increases. note 7: guaranteed by 100% production test at elevated temperature for a shorter time; equivalence of this production test to datasheet limit at operating temperature range is established by reliability testing. note 8: eeprom writes can become nonfunctional after the data retention time is exceeded. long-time storage at elevated tem-peratures is not recommended; the device can lose its write capability after 10 years at +125? or 40 years at +85?. note 9: all values are referred to v ih(min) and v il(max) levels. note 10: see figure 3. note 11: c b = total capacitance of one bus line in pf. if mixed with high-speed-mode devices, faster fall times according to i 2 c bus specification v2.1 are allowed. electrical characteristics (continued)(t a = -40? to +85?.) (note 1) parameter symbol conditions min typ max units v cc 2.0v 20 + 0.1c b 250 output fall time from v ih(min) to v il(max) with a bus capacitance from 10pf to 400pf (notes 2, 11) t of v cc < 2.0v 20 + 0.1c b 300 ns pulse width of spikes that are suppressed by the input filter t sp (note 2) 50 ns input current with an input voltage between 0.1v cc and 0.9v ccmax i i (note 12) -10 +10 a input capacitance c i (note 2) 10 pf scl clock frequency f scl (note 13) 400 khz bus timeout t timeout cm bit = 1 (note 13) 25 75 ms hold-time (repeated) start condition; after this period, the first clock pulse is generated t hd:sta (note 14) 0.6 s v cc 2.7v 1.3 v cc 2.0v 1.5 low period of the scl clock (note 14) t low v cc < 2.0v 1.9 s high period of the scl clock t high (note 14) 0.6 s setup time for a repeated start condition t su:sta (note 14) 0.6 s v cc 2.7v 0.3 0.9 v cc 2.0v 0.3 1.1 data hold time (notes 15, 16) t hd:dat v cc < 2.0v 0.3 1.5 s data setup time t su:dat (notes 2, 14, 17) 100 ns setup time for stop condition t su:sto (note 14) 0.6 s bus free time between a stop and start condition t buf (note 14) 1.3 s capacitive load for each bus line c b (notes 2, 14) 400 pf 1kb i 2 c/smbus eeprom with sha-1 engine _______________________________________________________________________________________ 3 abridged data sheet downloaded from: http:///
DS28CN01 note 12: the DS28CN01 does not obstruct the sda and scl lines if v cc is switched off. note 13: the minimum scl clock frequency is limited by the bus timeout feature. if the cm bit is 1 and scl stays at the same logic level or sda stays low for this interval, the DS28CN01 behaves as though it has sensed a stop condition. note 14: system requirement. note 15: the DS28CN01 provides a hold time of at least 300ns for the sda signal (referred to the v ih(min) of the scl signal) to bridge the undefined region of the falling edge of scl. note 16: the master can provide a hold time of 0ns minimum when writing to the device. this 0ns minimum is guaranteed bydesign, characterization, and/or simulation only, and not production tested. note 17: a fast-mode i 2 c bus device can be used in a standard-mode i 2 c bus system, but the requirement t su:dat 250ns must then be met. this is automatically the case if the device does not stretch the low period of the scl signal. if such a devicedoes stretch the low period of the scl signal, it must output the next data bit to the sda line t rmax + t su:dat = 1000 + 250 = 1250ns (according to the standard-mode i 2 c bus specification) before the scl line is released. 1kb i 2 c/smbus eeprom with sha-1 engine 4 _______________________________________________________________________________________ abridged data sheet pin description pin name function 1 ad0 device address input pin to select the slave address. sets slave address bits a[1:0] and must be connected to either gnd, sda, scl, or v cc . 2 ad1 device address input pin to select the slave address. sets slave address bits a[3:2] and must be connected to either gnd, sda, scl, or v cc . 3, 7 n.c. no connection 4 gnd ground supply 5 sda i 2 c/smbus bidirectional serial data line. this pin must be connected to v cc through a pullup resistor. 6 scl i 2 c/smbus serial clock input. this pin must be connected to v cc through a pullup resistor. 8 v cc power-supply input detailed description the DS28CN01 features a serial i 2 c/smbus interface, 1kb of sha-1 secure eeprom, a register page, and aunique registration number, as shown in the block diagram . the device communicates with a host proces- sor through its i 2 c interface in standard mode or in fast mode. the user can switch the interface from i 2 c bus mode to smbus mode. two 4-level address pins allow16 DS28CN01s to reside on the same bus segment. device operation read and write access to the DS28CN01 is controlledthrough the i 2 c/smbus serial interface. since the DS28CN01 has memory areas and registers of differentcharacteristics, there are several special cases to con- sider. see the read and write section in the full data sheet for details. serial communication interface the serial interface uses a data line (sda) plus a clocksignal (scl) for communication. both sda and scl are bidirectional lines, connected to a positive supply volt- age through a pullup resistor. when there is no commu- nication, both lines are high. the output stages of devices connected to the bus must have an open-drain or open-collector output to perform the wired-and function. data can be transferred at rates of up to 100kbps in the standard mode, and up to 400kbps in the fast mode. the DS28CN01 works in both modes. a device that sends data on the bus is defined as a transmitter and a device receiving data is a receiver. the device that controls the communication is called a master. the devices that are controlled by the master are slaves. the DS28CN01 is a slave device. electrical characteristics (continued)(t a = -40? to +85?.) (note 1) downloaded from: http:///
DS28CN01 1kb i 2 c/smbus eeprom with sha-1 engine _______________________________________________________________________________________ 5 DS28CN01 i 2 c/smbus function control memory and sha-1 engine control mac comparator mac output buffer 8-byte write buffer 64-bit unique number sha-1 engine secret memory register page user eeprom 4 pages of 32 bytes scl v cc sda ad_ block diagram slave address/direction byte to be individually accessed, each device must have aslave address that does not conflict with other devices on the bus. the slave address to which the DS28CN01 responds is shown in figure 1. the slave address is part of the slave-address/direction byte. the upper 3 bits of the DS28CN01 slave address are set to 101b. the ad0 pin controls address a0 and a1; ad1 controls a2 and a3. ad0 and ad1 can be connected to gnd, v cc , scl, or sda. table 1 shows the translation of these four pin states to binary addresses. to be select-ed, the device must be addressed with a0 to a3 match- ing the binary address of the respective pins. the last bit of the slave-address/direction byte (r/ w ) defines the data direction. when set to a 0, subsequentdata flows from master to slave (write-access mode); when set to a 1, data flows from slave to master (read- access mode). 1 a6 msb 0 a5 1 a4 ad1 a3 7-bit slave address a2 a1 ad0 a0 r/w determines read or write 4-level pin states (see the slave address/direction byte section) figure 1. slave address ad1 a3 a2 ad0 a1 a0 gnd 0 0 gnd 0 0 v cc 0 1 v cc 0 1 scl 1 0 scl 1 0 sda 1 1 sda 1 1 table 1. pin state to binary translation abridged data sheet downloaded from: http:///
DS28CN01 1kb i 2 c/smbus eeprom with sha-1 engine 6 _______________________________________________________________________________________ sda scl idle 1? 8 9 1? 8 9 1? 8 9 start condition stop condition repeated start slave address r/w ack ack data ack/ nack data msb first msb lsb msb lsb repeated if more bytes are transferred figure 2. i 2 c/smbus protocol overview i 2 c/smbus protocol data transfers can be initiated only when the bus is notbusy. the master generates the scl, controls the bus access, generates the start and stop conditions, and determines the number of bytes transferred on the sda line between start and stop. data is transferred in bytes with the most significant bit being transmitted first. after each byte, an acknowledge bit follows to allow synchronization between master and slave. during any data transfer, sda must remain stable whenever the clock line is high. changes in the sda line while scl is high are interpreted as a start or a stop. the protocol is illustrated in figure 2. see figure 3 for detailed timing references. bus idle or not busy both sda and scl are inactive, i.e., in their logic-high states. start condition to initiate communication with a slave, the master must generate a start condition. a start condition is defined as a change in state of sda from high to low while scl remains high. stop condition to end communication with a slave the master must generate a stop condition. a stop condition is defined as a change in state of sda from low to high while scl remains high. repeated start conditionrepeated starts are commonly used for read access- es after having specified a memory address to read from in a preceding write access. the master can use a repeated start condition at the end of a data transfer to immediately initiate a new data transfer following the current one. a repeated start condition is generated the same way as a normal start condition, but without a preceding stop condition. data valid with the exception of the start and stop condition, transitions of sda can occur only during the low state of scl. the data on sda must remain valid and unchanged during the entire high pulse of scl plus the required setup and hold time (t hd:dat after the falling edge of scl and t su:dat before the rising edge of scl; see figure 3). there is one clock pulse per bit ofdata. data is shifted into the receiving device during the rising edge of the scl pulse. when finished with writing, the master must release the sda line for a sufficient amount of setup time (minimum t su:dat + t r in figure 3) before the next rising edge of scl to start reading. the slave shifts out each data biton sda at the falling edge of the previous scl pulse and the data bit is valid at the rising edge of the current scl pulse. the master generates all scl clock pulses, including those needed to read from a slave. abridged data sheet downloaded from: http:///
acknowledged by slavea slave device, when addressed, is usually obliged to generate an acknowledge after the receipt of each byte. the master must generate the clock pulse for each acknowledge bit. a slave that acknowledges must pull down the sda line during the acknowledge clock pulse so that it remains stable low during the high peri- od of this clock pulse. setup and hold times t su:dat and t hd:dat must be taken into account. acknowledged by masterto continue reading from a slave, the master is obliged to generate an acknowledge after the receipt of each byte. the master must generate the clock pulse for each acknowledge bit. a master that acknowledges must pull down the sda line during the acknowledge clock pulse so that it remains stable low during the high period of this clock pulse. setup and hold times t su:dat and t hd:dat must be taken into account. not acknowledged by slavea slave device may be unable to receive or transmit data either because of an invalid access mode, because the sha-1 engine is running, or because a eeprom write cycle is in progress. in this case, theDS28CN01 does not acknowledge any bytes that it refuses by leaving sda high during the high period of the acknowledge-related clock pulse. see the read and write section in the full data sheet for a detailed list of situations where the DS28CN01 does not acknowl-edge. not acknowledged by master at some time when receiving data, the master must ter- minate a read access. to achieve this, the master does not acknowledge the last byte that it has received from the slave by leaving sda high during the high period of the acknowledge-related clock pulse. in response, the slave stops transmitting, allowing the master to gener- ate a stop condition. data memory and registers for this section including figures 4 and 5 and table 2,refer to the full version of the data sheet. read and write this section discusses the read and write behavior of the eeprom and the various registers. refer to the full data sheet for details, including tables 3 to 13. DS28CN01 1kb i 2 c/smbus eeprom with sha-1 engine _______________________________________________________________________________________ 7 sclnote: timing is referenced to v il(max) and v ih(min) . sda stop start repeated start t buf t hd:sta t hd:dat t su:dat t su:sto t hd:sta t sp t su:sta t high t r t f t low figure 3. i 2 c/smbus timing diagram abridged data sheet downloaded from: http:///
DS28CN01 sha-1 computation algorithm this description of the sha-1 computation is adaptedfrom the secure hash standard sha-1 document that can be downloaded from the nist website. refer to the full version of the data sheet for more details. applications information sda and scl pullup resistors sda is an open-drain output on the DS28CN01 thatrequires a pullup resistor (see the typical operating circuit ) to realize high logic levels. because the DS28CN01 uses scl only as input (no clock stretch-ing), the master can drive scl either through an open- drain/collector output with a pullup resistor or a push-pull output. pullup resistor r p sizing according to the i 2 c specification, a slave device must be able to sink at least 3ma at a v ol of +0.4v. the smbus specification requires a current sink capabilityof 4ma at +0.4v. the DS28CN01 can sink at least 4ma at +0.4v v ol over its entire operating voltage range. this dc characteristic determines the minimum value ofthe pullup resistor: r pmin = (v cc - 0.4v)/4ma. with a maximum operating voltage of +5.5v, the minimum value for the pullup resistor is 1.275k . the ?inimum r p ?line in figure 6 shows how the minimum pullup resistor changes with the operating (pullup) voltage.for i 2 c systems, the rise time and fall time are mea- sured from 30% to 70% of the pullup voltage. the maxi-mum bus capacitance c b is 400pf. the maximum rise time must not exceed 300ns. assuming maximum risetime, the maximum resistor value at any given capaci- tance c b is calculated as: r pmax = 300ns/(c b x ln(7/3)). for a bus capacitance of 400pf the maximumpullup resistor would be 885 . since an 885 pullup resistor, as would be required to meet the rise time specification and 400pf bus capaci-tance, is lower than r pmin at +5.5v, a different approach is necessary. the ?aximum load?line infigure 6 is generated by first calculating the minimum pullup resistor at any given operating voltage (?inimum r p ?line) and then calculating the respective bus capacitance that yields a rise time of 300ns.only for pullup voltages of +4v and lower can the maxi- mum permissible bus capacitance of 400pf be main- tained. a reduced bus capacitance of 300pf is acceptable for the entire operating voltage range. the corresponding pullup resistor value at the voltage is indicated by the ?inimum r p ?line. 1kb i 2 c/smbus eeprom with sha-1 engine 8 _______________________________________________________________________________________ abridged data sheet minimum r p ( ) load (pf) pullup voltage (v) 1.5 2.0 2.5 3.0 3.5 4.0 4.5 5.0 5.5 1200 600 1000 500 800 400 600 300 400 200 200 100 0 0 minimum r p maximum load at minimum r p fast mode figure 6. i 2 c fast-mode pullup-resistor selection chart downloaded from: http:///
DS28CN01 1kb i 2 c/smbus eeprom with sha-1 engine _______________________________________________________________________________________ 9 abridged data sheet r p r p v cc c sda to additional devices scl v cc gnd sda sclad1 ad0 v cc gnd DS28CN01 typical operating circuit package type package code document no. 8 ?op u8+3 21-0036 package information for the latest package outline information and land patterns, go to www.maxim-ic.com/packages . note that a ?? ?? or ??in the package code indicates rohs status only. package drawings may show a different suffix character, but the drawing pertains to th e package regardless of rohs status. downloaded from: http:///
DS28CN01 1kb i 2 c/smbus eeprom with sha-1 engine abridged data sheet maxim cannot assume responsibility for use of any circuitry other than circuitry entirely embodied in a maxim product. no circuit patent licenses are implied. maxim reserves the right to change the circuitry and specifications without notice at any time. 10 ____________________maxim integrated products, 120 san gabriel drive, sunnyvale, ca 94086 408-737-7600 2009 maxim integrated products maxim is a registered trademark of maxim integrated products, inc. revision history revision number revision date description pages changed 0 6/07 initial release. 1 4/09 created newer template-style data s heet. all 2 11/09 added condition cm bit = 1 to the bus timeout specification in the elecrical characerisics . 3 downloaded from: http:///
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